Variable delay circuit having a ramp voltage generating unit

ABSTRACT

A variable delay circuit includes a ramp voltage generating unit having a storage capacitor, a charging transistor for charging the capacitor and a constant-current source for discharging the capacitor, and a comparator for comparing the output of the ramp voltage generating circuit against a voltage setting to output a delayed signal. The electric charge flowing out from the output node of the ramp voltage generating unit through the charging transistor during generating the ramp voltage is compensated by a compensating capacitor to output a linear ramp voltage.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a variable delay circuit havinga ramp voltage generating unit, and more particularly to ahigh-performance variable delay circuit which generates delay timesfollowing the settings with excellent linearity.

[0003] 2. Description of the Related Art

[0004] In recent years, capability of higher time resolution measurementhas been required of LSI testers along with the higher speed operationof LSIs to be measured. The minimum time resolution (1 LSB) is on itsway to falling below 10 pico-second (Ps). Moreover, LSI testers formeasuring LSI absolute performance must have a sufficiently highaccuracy guaranteed. Typically, the degree of accuracy requirements forthe time resolution is 1 LSB or smaller. The variable delay time usedfor the time resolution measurement is generated by a known variabledelay circuit having a ramp voltage generating unit. For the sake ofsufficiently high accuracy, the linearity of the delay time with respectto settings is of importance. Since the linearity of the delay timedepends on the linearity of the ramp voltage waveform, it is importantto generate the ramp voltage with superior linearity. As used herein,the term “ramp voltage” refers to a signal voltage having a waveformwherein the amplitude varies or changes linearly in proportion to time.

[0005]FIG. 1 is a circuit diagram of a variable delay circuit describedin Japanese Patent Laid-Open Publication No. Hei 8-181584. Nodes N11 andN12 receive differential signals which are complementary to each other.It is assumed here that the logic on the node N11 is the positive logic.A node N19 receives an arbitrary voltage setting which falls within therange of the amplitude on a ramp voltage generating node 16. WhenH-level and L-level are input to the node N11 and the node N12,respectively, an NPN transistor Q11 turns ON and an NPN transistor Q12turns OFF. As a result, a node N13 turns to H-level. Thus, an NPNtransistor Q13 turns ON to charge a storage capacitor C11, therebyraising the potential of the node N16 to H-level. The storage capacitorC11 is charged steeply in a very short time after the potential changeof the node N13 due to the large driveability of the NPN transistor Q13.

[0006] Feed of L-level to the node N11 and H-level to the node N12 turnsthe NPN transistor Q11 OFF and the NPN transistor Q12 ON. Thus, the nodeN13 turns to L-level. Here, the NPN transistor Q13 turns OFF since thenode N16 is held at the H-level by the charge stored in the capacitor.The charge stored in the storage capacitor C11 is gradually dischargedat a constant rate through a constant-current source 15. Due to theconstant rate of the discharge, the potential of the node N16 traces aramp voltage waveform which declines linearly in proportion to time.When the ramp voltage falls below the potential input to the node N19, acomparator 16 turns its output potential on a node N17 from H-level toL-lvel. The voltage setting input to the node N19 can be changed tomodify the time instant at which the potential of the ramp voltage fallsbelow the potential input to the node N19. The voltage setting for thenode N19 achieves variation of the delay time.

[0007]FIG. 2 shows potential changes on some of the nodes in the circuitdiagram of FIG. 1. For convenience of description, the delay variationis shown in seven levels. It is to be noted however that the knownhigh-performance variable delay circuits usually have a greater numberof variation levels.

[0008] The node N19 receives any one of arbitrary voltage settings V1 toV7. The potential of the node N17 falls from H-level to L-level at anyof the time instants t1 to t7 at which the potential of the node N16falls below the potential of the node N19. The time interval between thetime t0 at which the node N11 falls and any one of the times t1 to t7 atwhich the node N17 falls based on the voltage settings V1 to V7 is thedelay time generated by the variable delay circuit. The time intervalbetween the time t1 and the time t7 is the span of the variable delaytime.

[0009] In the variable delay circuit described in the above publication,as described above, the charge stored in the storage capacitor C11 isdischarged through the constant-current source 15. In the discharge, thewaveform of the node N13 does not trace an ideal rectangular waveformand falls from H-level to L-level with a significant deformation(deterioration). Thus, during the potential fall of the node 16, thecapacitor-charging transistor Q13 is subjected to a voltage that varieswith time, across its base and emitter. It is to be noted that there isa parasitic capacitance Cje11 between the base and emitter of thecapacitor-charging transistor Q13, which means that the voltage acrossthis parasitic capacitance Cje11 varies also. The variation of thevoltage across the parasitic capacitance Cje11 causes storage of chargein this parasitic capacitance. This impedes the charge in the storagecapacitor C11 from decreasing at a constant rate, thereby degrading thelinearity of the ramp voltage. The waveform shown in FIG. 2 has asignificant deterioration in the linearity thereof. In this connection,the straight, broken line in FIG. 2 shows a ramp voltage without anylinearity deterioration that results from the storage of charge in theparasitic capacitance Cje11 of the capacitor-charging transistor Q13.

[0010]FIGS. 3A and 3B are a graph showing the characteristic of thedelay time generated by the variable delay circuit of FIG. 1 and a graphshowing the amount of deterioration of the delay time from the straightline, respectively. The delay time loses its linearity while thepotential of the node N13 in FIG. 1 changes from H-level to L-level.

[0011]FIG. 4 shows how the ramp voltage in the variable delay circuitshown in FIG. 1 deteriorates in linearity due to the parasiticcapacitance, illustrating (a) potential of the node N13, (b)base-to-emitter voltage of the transistor Q13, (c) charge in theparasitic capacitor Cje11 and (d) potential of the node N16. The diagramspecifically shows the time interval from the time instant t0 when thewaveform of the node N13 starts its fall to the time instant tm when thewaveform of the node N13 completes the change to L-level, during whichthe charge flows on the node 16 into the parasitic capacitance Cje11 ofthe capacitor-charging transistor Q13 to cause a deterioration in thelinearity of the ramp voltage. The voltage across the parasiticcapacitance Cje11 continues to change until the ramp voltage reachesL-level. A linear change of the voltage, however, results in a linearoutflow of the charge in the parasitic capacitor Cje11 through theconstant-current source 15 after the time instant tm, thereby causing nosignificant deterioration in this period in the linearity of the rampvoltage.

[0012] Among the possible prevention measures against the linearitydeterioration, a method may be adopted by forming the storage capacitorC11 to have a larger capacitance and increasing the current flowingthrough the constant-current source 15 so that the influence of thecharge flow into the parasitic capacitance Cje11 of thecapacitor-charging transistor Q13 decreases in the proportion to thewhole current. If the measure by this method is adopted, however, theupsizing of the capacitor causes an increase in circuit scale, and therise of the current yields an increase in power dissipation. Higherintegration and multi-function of LSIs in the trend of recent yearsincrease the numbers of pins on the LSIs to be measured and advance themeasurement coverage. This trend also necessitates higher integrationand lower power dissipation even in the tester LSIs. In light of theserequirements, the increases in circuit scale and power dissipation areunacceptable. Furthermore, this measure provides merely a reduction ofthe proportion of deterioration to the whole, and the linearitydeterioration still occurs, without providing any essential solution.

SUMMARY OF THE INVENTION

[0013] It is an object of the present invention to provide an essentialsolution to the problem of the conventional art described above, and toprovide a high-performance variable delay circuit having a higherlinearity.

[0014] The present invention provides, in a first aspect thereof, avariable delay circuit including a signal input unit for receiving aninput signal to output a first signal through a first node, a rampvoltage generating unit for generating a ramp voltage on a ramp voltageoutput node, the ramp voltage generating circuit including a storagecapacitor for storing electric charge on the ramp voltage output node, acharging transistor for responding to the first signal to charge theramp voltage output node, and a constant-current source for dischargingthe ramp voltage output node at a constant rate, a comparator forcomparing the ramp voltage against a voltage setting to output a delayedsignal which is delayed from the input signal by a delay timecorresponding to the voltage setting, and a compensating unit forcompensating electric charge flowing from the ramp voltage output nodeinto a parasitic capacitance of the charging transistor.

[0015] The present invention provides, in a second aspect thereof, avariable delay circuit comprising a signal input unit for receiving aninput signal to output a first signal through a first node, a rampvoltage generating unit for generating a ramp voltage on a ramp voltageoutput node, the ramp voltage generating circuit including a storagecapacitor for storing electric charge on the ramp voltage output node, adischarging transistor for responding to the first signal to dischargethe ramp voltage output node, and a constant-current source for chargingthe ramp voltage output node at a constant rate, a comparator forcomparing the ramp voltage against a voltage setting to output a delayedsignal which is delayed from the input signal by a delay timecorresponding to the voltage setting, and a compensating unit forcompensating electric charge flowing from the ramp voltage output nodeinto a parasitic capacitance of the discharging transistor.

[0016] In accordance with the variable delay circuit of the presentinvention, the compensation unit compensates the electric charge flowinginto the parasitic capacitance of the charging or discharging transistorto store electric charge in the parasitic transistor, therebymaintaining a high linearity of the ramp voltage waveform, whereby thedelay times output from the variable delay circuit follow the voltagesettings with an excellent linearity.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIG. 1 is a circuit diagram of a conventional variable delaycircuit;

[0018]FIG. 2 is a timing chart of the potentials of nodes in thevariable delay circuit of FIG. 1;

[0019]FIGS. 3A and 3B are diagrams showing the characteristic of thedelay time and the non-linearity of the delay time, respectively, of thevariable delay circuit of FIG. 1;

[0020]FIG. 4 is a timing chart for showing linearity deterioration inthe ramp voltage caused by the parasitic capacitance in the variabledelay circuit of FIG. 1;

[0021]FIG. 5 is a circuit diagram showing a variable delay circuitaccording to a first embodiment of the present invention;

[0022]FIG. 6 is a timing chart of the potentials of nodes in thevariable delay circuit of FIG. 5;

[0023]FIGS. 7A and 7B are diagrams showing the characteristics of thevariable delay time and the non-linearity of the delay time,respectively, of the variable delay circuit of FIG. 5;

[0024]FIG. 8 is a circuit diagram showing a variable delay circuitaccording to a second embodiment;

[0025]FIG. 9 is a circuit diagram showing a variable delay circuitaccording to a third embodiment;

[0026]FIG. 10 is a circuit diagram showing a variable delay circuitaccording to a fourth embodiment;

[0027]FIG. 11 is a circuit diagram showing a variable delay circuitaccording to a fifth embodiment;

[0028]FIG. 12 is a circuit diagram showing a variable delay circuitaccording to a sixth embodiment;

[0029]FIG. 13 is a circuit diagram showing a variable delay circuitaccording to a seventh embodiment; and

[0030]FIG. 14 is a circuit diagram showing a variable delay circuitaccording to an eighth embodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] Hereinafter, the variable delay circuit of the present inventionwill be described in conjunction with the embodiments of the presentinvention and with reference to the drawings, wherein similarconstituent elements are designated by similar reference numeralsthroughout the drawings.

[0032] Referring to FIG. 5, there is shown a variable delay circuitaccording to a first embodiment of the present invention. The variabledelay circuit of the present embodiment includes an amplifying bufferunit 11, a ramp voltage generating unit 12, a comparator unit 13, and acompensation unit 17. The amplifying buffer unit 11 is a differentialcircuit which is composed of an emitter-coupled-logic circuit includingNPN transistors Q11 and Q12, a constant-current source 14, and resistorsR11 and R12. The amplifying buffer unit 11 is used as an input circuitsection. The ramp voltage generating unit 12 is composed of acapacitor-charging NPN transistor Q13, a constant-current source 15, anda storage capacitor C11. The comparator unit 13 is composed of acomparator 16 and a voltage setting input node N19. The compensationunit 17 is composed of an NPN transistor Q14 which is used forcompensating the parasitic capacitor.

[0033] The base and collector of the NPN transistor Q11 are connected tonodes N11 and N14, respectively. The base and collector of the NPNtransistor Q12 are connected to nodes N12 and N13, respectively. The NPNtransistors Q11 and Q12 have respective emitters connected together at anode N15. The node N15 is connected to one of the terminals of theconstant-current source 14 which is grounded at its other terminal. Thenode N14 is connected to one of the terminals of the resistor R12 whichis connected to a power supply line VCC at the other terminal. The nodeN13 is connected to one of the terminals of the resistor R11 which isconnected to the power supply line VCC at the other terminal.

[0034] The node N13 is connected to the base of the NPN transistor Q13which operates as a capacitor charging transistor. The collector of theNPN transistor Q13 is connected to the power supply line VCC. Theemitter of the same is connected to a ramp voltage generating node, or anode N16. This node N16 is connected to the inflow-side terminal of thecapacitor discharging constant-current source 15 and either one terminalof the storage capacitor C11. The discharge terminal of theconstant-current source 15 and the other terminal of the storagecapacitor C11 are grounded.

[0035] The node N16, or the ramp voltage generating node, is connectedto the non-inverting input of the comparator 16. The inverting input ofthe comparator 16 receives a voltage setting. The NPN transistor Q14 tobe used as the compensating element is connected at its base to the nodeN16, the ramp voltage generating node. The emitter of the NPN transistorQ14 is connected to the node N14 from which the inverted logic of thenode N13 is obtained. The collector of the same is connected to thepower supply line VCC.

[0036] The NPN transistors Q13 and Q14 have the same structure and thesame size, with parasitic capacitances Cje11 and Cje12 being involvedbetween their bases and emitters, respectively. In general, parasiticcapacitances have absolute variations from design values under theinfluence of process conditions, whereas they have very little relativevariations within a single LSI and the LSIs formed under the sameprocess conditions.

[0037] The resistors R12 and R11 have the same structure and the samesize, and accordingly the same resistance. The node N19, or theinverting input of the comparator 16, is supplied with a voltage settingselected from a plurality of voltage settings. For example, the node N19is connected to the output of a digital-to-analog converter (DAC) whichis not shown in the drawing. A digital, arbitrary setting value is inputto the DAC so that an analog voltage on the basis of the setting isinput to the node N19 from the DAC. The output potential of the DACshall vary linearly with sufficient accuracy to the digital input signalfed to the DAC.

[0038] The node N17 and/or N18 is connected to an external circuit. Thenodes N11 and N12 receive differential signals which are complementaryto each other. It is assumed here that the logic on the node N11 is thepositive logic. The node N19 receives an arbitrary voltage that falls onany potential within the range of amplitude of the ramp wave generatingnode. Inputting H-level to the node N11 and L-level to the node N12turns the NPN transistor Q11 ON and the NPN transistor Q12 OFF. Thus,the node N13 turns to H-level. Then, the NPN transistor Q13 turns ON tocharge the storage capacitor C11, raising the potential of the node N16to H-level. The storage capacitor C11 is charged steeply in a very shorttime after the potential change of the node N13.

[0039] Inputting L-level to the node N11 and H-level to the node N12turns the NPN transistor Q11 OFF and the NPN transistor Q12 ON. Thus,the node N13 turns to L-level. The NPN transistor Q13 then turns OFFsince the node N16 is held at the H-level by the charge stored in thestorage capacitor C11. The charge stored in the storage capacitor C11 isgradually discharged at a constant rate through the constant-currentsource 15. Due to the constant rate of the discharge, the potential ofthe node N16 traces or follows a ramp voltage waveform which declineslinearly in proportion to time. When this ramp voltage falls below thepotential input to the node N19, the comparator 16 turns its outputpotential from H-level to L-level. The voltage setting input to the nodeN19 can be changed to modify the time instant at which the potential ofthe ramp voltage falls below the potential input to the node N19. Thisvoltage setting achieves the variation of the delay time.

[0040] When L-level and H-level are input to the nodes N11 and N12,respectively, the NPN transistor Q13 is turned OFF so that the potentialof the node 16 falls along a ramp voltage. The node N13 falls fromH-level to L-level at an operating speed that is determined by thedriveability of the amplifying buffer unit 11. The time instant at whichthe node N16 starts to generate a ramp voltage substantially coincideswith the time instant at which the node N13 starts to fall. The timeinstant at which the node N13 stops fall, however, precedes the end timeof the ramp voltage. As a result, the voltage across the base andemitter of the capacitor-charging transistor Q13 changes to therebychange the charge stored in the parasitic capacitance Cje11 involvedbetween the nodes N13 and N16. This means that the charge flows out ofthe ramp voltage generating node N16 into the parasitic capacitanceCje11.

[0041] In the mean time, the potential of the node N14 rises fromL-level to H-level. The signal change of the node N14 is opposite tothat of the node N13 in terms of logical polarity, and identical theretoin terms of time instant. Thus, as in the case of the node N13, the rampstart time of the node N16 and the rise start time of the node N14coincide with each other. The end times thereof are, however, differentfrom each other, which means that the voltage across the emitter andbase of the compensating transistor Q14 changes with time. The chargestored in the parasitic capacitance Cje12 also changes, the parasiticcapacitance Cje12 being involved between the nodes N14 and N16, i.e.,emitter and base of the transistor Q14 as in the case of transistor Q13.This means that the charge flows out of the parasitic capacitance Cje12into the ramp voltage generating node N16.

[0042] Here, the charge that flows into the node 16 from the parasiticcapacitance Cje12 and the charge that flows from the node 16 into theparasitic capacitance Cje11 are equal to each other in amount, therebycompensating each other to result in a total sum of zero. Since thereoccurs no change of the total electric charge other than that caused bythe discharge through the constant-current source 15, the ramp voltagefollows an ideal linear characteristic with respect to time.

[0043]FIG. 6 shows the relationship between the potentials of nodes inthe variable delay circuit of FIG. 5. For convenience of description,the delay time is shown as adjusted in seven levels. It is to be notedthat the high-performance variable delay circuits shown in the presentinvention usually have a greater number of variation levels. At the timeinstant when the input signal fed to the node N11 falls from H-level toL-level, the potential of the node N16 starts to fall along a rampvoltage waveform that declines at a constant rate. When the ramp voltagebecomes lower than (or equal to) the voltage setting input to theinverting input of the comparator 16, the output potential of the nodeN17, or an output of the comparator 16, falls from H-level to L-level.The output node N17 falls at one of the time instants t1 to t7, with thedelay time thereof corresponding to one of the voltage settings V1 toV7.

[0044] The time interval between the time instant t0 at which the nodeN11 falls and any one of the time instants t1 to t7 at which the signalsdelayed in accordance with the voltage settings V1 to V7 are output isthe total delay time generated by the variable delay circuit. The timeinterval between the time instant t1 and the time instant t7 is the spanof the variable delay times.

[0045] Referring to FIGS. 7A and 7B, there are shown a graph depictingthe characteristic of the delay time with respect to the voltage settingin the variable delay circuit of FIG. 1, and a graph depicting theamount of deviation of the delay time from the straight line withrespect to the voltage setting, respectively. The variable delay circuitof the present embodiment produces substantially no deterioration fromthe straight line due to the cancellation as described above.

[0046] Now the principle of the present invention will be described withreference to comparison with the conventional variable delay circuit ofFIG. 1, wherein the compensating unit of the embodiment is not used. Itis assumed here that the minimum resolution 1 LSB=10 ps, and the rampvoltage amplitude is 800 mV. Then, on the assumptions that thecapacitor-charging transistor has a parasitic capacitance Cje11 of 5 fF,that the time for the output of the amplifying buffer unit 11, or forthe signal input to the base of the capacitor-charging transistor Q13,to change from H-level to L-level is half the time for the ramp voltageto change from H-level to L-level, and that 1 ns elapses from the startto the end of the ramp voltage, then the ramp voltage falls 24.4 mVbelow the straight line. This translates into a decrease of 31 ps in thedelay time. Since the minimum resolution 1 LSB is 10 ps, the value meansthat the integral non-linearity (INL) reaches as high as 3.1 LSB. Theuse of the variable delay circuit of the present embodimentsubstantially eliminates this non-linearity.

[0047] If a conventional variable delay circuit with a greater capacitorand a higher current for the constant-current source, as describedbefore, is used so that the integrated non-linearity (INLΔ assumes avalue lower than or equal to the minimum resolution 1 LSB, or 10 ps, thestorage capacitor C11 must be 3.1 times greater in size or more.Besides, the current must be 3.1 times higher or more. As describedbefore, corresponding to the increased numbers of pins on LSIs to bemeasured and the advanced measurement coverage due to the higherintegration and multi-function of LSIs in recent years, higherintegration and lower power dissipation are also required of the testerLSIs. Under such circumstances, the above-mentioned increases in circuitscale and power dissipation are unacceptable.

[0048] Now, the conditions required for the linear characteristic of theramp voltage will be described below in conjunction with generalequations. In the following description, C stands for the capacitance ofthe storage capacitor C11, Q for the amount of charge stored in thestorage capacitor C11, and V for the voltage across the storagecapacitor C11, There holds a general equation (1):

V=Q/C  (1).

[0049] From the equation (1), it is found that the voltage V across thestorage capacitor C11 is proportional to the amount of charge Q if thecapacitance C is constant.

[0050] If the storage capacitor C11 is to be charged by aconstant-current source, then Q, the amount of charge stored in thecapacitor, is given by the equation (2):

Q=I×t   (2),

[0051] where I is the current of the constant-current source 15, and tis the time elapsed from the start of charge, assuming that the amountof initial charge is zero. The case where an initial charge of Qm isdischarged through the constant-current source of I, there holds theequation (3):

Q=(Qm−I×t)  (3).

[0052] In the variable delay circuit, the amount of charge Qm stored inthe storage capacitor C11 is discharged through the constant-currentsource of I. To show the relation as a time function, the voltage V istranslated into a time-based equation V(t), or the equation (4) that isobtained from the equations (1)-(3):

V(t)=(Qm−I×t)/C  (4).

[0053] As can be seen from the equation (4), the voltage V(t) across thestorage capacitor C11 changes linearly in proportion to the time t ifthe current I is constant. It will be understood, however, thatintroduction of extraneous factors that change the charge stored in thestorage capacitor C11 can impede V(t) from being proportional to thetime t. The present invention solves the above problem by canceling thechange of charge stored in the storage capacitor C11, as describedbefore.

[0054] Referring to FIG. 8, there is shown a variable delay circuitaccording to a second embodiment. The variable delay circuit of thepresent embodiment is similar to the first embodiment except that acompensating capacitor C12 is connected as the compensating unit 17Abetween the ramp voltage generating node N16 and the node N14, insteadof the NPN transistor Q14 shown in FIG. 1. The capacitor C12 to be usedfor compensation has the same capacitance as the base-to-emitterparasitic capacitance Cje11 in the capacitor-charging transistor Q13.The operations and functions are identical to those of the firstembodiment.

[0055] According to the present embodiment, wherein the capacitor C12 isused as the compensating element instead of the bipolar transistor, thecircuit configuration can be simplified.

[0056] Referring to FIG. 9, there is shown a variable delay circuitaccording to a third embodiment. The variable delay circuit of thepresent embodiment is similar to the first embodiment except thatN-channel MOS (NMOS) transistors MN11 and MN12 are used in theamplifying buffer unit 11A, an NMOS transistor Mn13 is used in the rampvoltage generating circuit 12B, and an NMOS transistor Mn14 is used as acompensating unit 17B.

[0057] The variable delay circuit of the present embodiment has anadvantage of lower power dissipation, due to the inherentcharacteristics of the MOS transistor. In the variable delay circuit ofFIG. 5, the power supply voltage cannot be lowered due to thecollector-to-emitter voltage of the bipolar transistor necessitating ahigher power supply voltage. In contrast, the use of the MOS transistorsallows a decrease of the drain-to-source voltage without a malfunction,thereby permitting a lower power supply voltage to be employed.Moreover, there is an advantage of easier fabrication as compared withthe case where bipolar transistors are used.

[0058] In the circuit configuration of FIG. 10, the gate and drain ofthe NMOS transistor Mn11 are connected to nodes N11 and N14,respectively. The gate and drain of the NMOS transistor Mn12 areconnected to the nodes N12 and N13, respectively. The NMOS transistorsMn11 and Mn12 both are connected to the node N15 at their respectivesources. The node N15 is connected to the constant-current source 14which is grounded at its other terminal. The node N14 is connected toone of the terminals of the resistor R12 which is connected to the powersupply line VCC at the other terminal. The node N13 is connected to oneof the terminals of the resistor R11 which is connected to the powersupply line VCC at the other terminal.

[0059] The node N13 is connected to the gate of the NMOS transistor n13which operates as a capacitor-charging transistor. The drain of the NMOStransistor Mn13 is connected to the power supply line VCC. The source ofthe same is connected to the ramp voltage generating node N16. The nodeN16 is connected through the constant-current source 15 to the groundand connected to one of the terminals of the storage capacitor C11, theother terminal of which is connected to the ground. The node N16, or theramp voltage generating node, is connected to the non-inverting input ofthe comparator 16. The inverting input of the comparator 16 receives avoltage setting.

[0060] The NMOS transistor Mn14 used as the compensating element 17B isconnected at its gate to the ramp voltage generating node N16. Thesource of the NMOS transistor Mn14 is connected to a compensation signaloutputting terminal, or the node N14. The drain of the NMOS transistorMn14 is connected to the power supply line VCC. Here, instead of theMn14 to be used as the compensating element, a capacitor having the samecapacitance as the gate-to-source parasitic capacitance of thecapacitor-charging NMOS transistor Mn13 may be connected between thenode N14 and the node N16. The variable delay circuit having such acapacitor constitutes a fourth embodiment of the present invention. FIG.10 shows a circuit diagram thereof.

[0061] Referring to FIG. 11, there is shown a variable delay circuitaccording to a fifth embodiment. The variable delay circuit of thepresent embodiment is similar to the first embodiment except that PNPtransistors are sued instead of the NPN transistors in the firstembodiment. The delay time is generated at the time instant at which theramp voltage rises from L-level ot H-level.

[0062] In the circuit configuration of FIG. 11, the base and collectorof the PNP transistor Q15 are connected to the nodes N11 and N14,respectively. The base and collector of the PNP transistor Q16 areconnected to the nodes N12 and N13, respectively. The PNP transistorsQ15 and Q16 both are connected to the node N15 at their respectiveemitters. The node N15 is connected to the constant-current source 14which is connected to the power supply line VCC at its inflow-sideterminal. The node N14 is connected to one of the terminals of theresistor R12 which is grounded at the other terminal. The node N13 isconnected to one of the terminals of the resistor R11 which is groundedat the other terminal.

[0063] The node N13 is connected to the base of the PNP transistor Q18which operates as a capacitor-discharging transistor. The collector ofthe PNP transistor Q18 is grounded. The emitter of the same is connectedto the ramp voltage generating node, or node N16. This node N16 isconnected to the outflow-side terminal of the constant-current source 15for charging the storage capacitor C11 and either one terminal of thestorage capacitor C11. The inflow-side terminal of the constant-currentsource 15 is connected to the power supply line VCC. The other terminalof the storage capacitor C11 is grounded. The node N16, or the rampvoltage generating node, is connected to the non-inverting input of thecomparator 16. The inverting input of the comparator 16 receives avoltage setting.

[0064] The PNP transistor Q18 used as the compensating unit 17D isconnected at its base to the ramp voltage generating node N16. Theemitter of the PNP transistor Q18 is connected to the compensationsignal outputting terminal, or the node N14. The collector of the PNPtransistor Q18 is grounded. Here, instead of the PNP transistor Q18 usedas the compensating unit 17B, a capacitor having the same capacitance asthe base-to-emitter parasitic capacitance of the capacitor-dischargingtransistor Q17 may be connected between the node N14 and the node N16.The variable delay circuit having such a capacitor constitutes a sixthembodiment of the present invention. FIG. 12 shows a circuit diagramthereof.

[0065] Referring to FIG. 13, there is shown a variable delay circuitaccording to a seventh embodiment of the present invention. The variabledelay circuit of the present embodiment is similar to the variable delaycircuit of FIG. 11 except that PMOS transistors are used instead of thePNP bipolar transistors.

[0066] In the circuit configuration of FIG. 13, the gate and drain ofthe PMOS transistor Mp11 are connected to the nodes N11 and N14,respectively. The gate and drain of the PMOS transistor Mp12 areconnected to the nodes N12 and N13, respectively. The PMOS transistorsMp11 and Mp12 both are connected to the node N15 at their respectivesources. The node N15 is connected to the constant-current source 14which is connected to the power supply line VCC at its inflow-sideterminal. The node N14 is connected to one of the terminals of theresistor R12 which is grounded at the other terminal. The node N13 isconnected to one of the terminals of the resistor R11 which is groundedat the other terminal.

[0067] The node N13 is connected to the gate of the PMOS transistor Mp13which operates as a capacitor-discharging transistor. The drain of thePMOS transistor Mp13 is grounded. The source of the same is connected tothe ramp voltage generating node, or node N16. The node N16 is connectedto the outflow-side terminal of the constant-current source 15 andeither one terminal of the storage capacitor C11. The inflow-sideterminal of the constant-current source 15 is connected to the powersupply line VCC. The other terminal of the storage capacitor C11 isgrounded. The node N16, or the ramp voltage generating node, isconnected to the non-inverting input of the comparator 16. The invertinginput of the comparator 16 receives a voltage setting.

[0068] The PMOS transistor Mp14 used as the compensating unit 17F isconnected at its gate to the ramp voltage generating node N16. Thesource of the PMOS transistor Mp14 is connected to the compensationsignal outputting terminal, or the node N14. The drain of the PMOStransistor Mp14 is grounded. Here, instead of the Mp14 used as thecompensating unit 17F, a capacitor having the same capacitance as thegate-to-source parasitic capacitance of the capacitor-dischargingtransistor Mp13 may be connected between the node N14 and the node N16.The variable delay circuit having such a capacitor constitutes an eighthembodiment of the present invention. FIG. 14 shows a circuit diagramthereof.

[0069] As has been described, according to the variable delay circuitsof the embodiments as described above, the compensation circuitcompensates as much electric charge as that flowing out of or into theparasitic capacitance in the charging or discharging transistor. Thismaintains the high linearity of the ramp voltage, thereby offering thedelay time with high linearity.

[0070] Since the above embodiments are described only for examples, thepresent invention is not limited to the above embodiments and variousmodifications or alterations can be easily made therefrom by thoseskilled in the art without departing from the scope of the presentinvention.

What is claimed is:
 1. A variable delay circuit comprising a signalinput unit for receiving an input signal to output a first signalthrough a first node, a ramp voltage generating unit for generating aramp voltage on a ramp voltage output node, said ramp voltage generatingcircuit including a storage capacitor for storing electric charge onsaid ramp voltage output node, a charging transistor for responding tosaid first signal to charge said ramp voltage output node, and aconstant-current source for discharging said ramp voltage output node ata constant rate, a comparator for comparing said ramp voltage against avoltage setting to output a delayed signal which is delayed from saidinput signal by a delay time corresponding to said voltage setting, anda compensating unit for compensating electric charge flowing from saidramp voltage output node into a parasitic capacitance of said chargingtransistor.
 2. The variable delay circuit as defined in claim 1 ,wherein said signal input unit is a differential circuit having a pairof complementary output nodes including said first node and a secondnode, and said compensating unit is a compensating capacitor connectedbetween said ramp voltage output node and said second node.
 3. Thevariable delay circuit as defined in claim 2 , wherein said chargingtransistor is an NPN transistor and said compensating capacitor isimplemented by a p-n junction reverse-biased between said ramp voltageoutput node and said second node.
 4. The variable delay circuit asdefined in claim 3 , wherein said p-n junction is implemented by baseand emitter of another NPN transistor having a design size equal to thatof said charging transistor.
 5. The variable delay circuit as defined inclaim 2 , wherein said charging transistor is an NMOS transistor.
 6. Thevariable delay circuit as defined in claim 5 , wherein said compensatingcapacitor is implemented by an NMOS capacitor.
 7. A variable delaycircuit comprising a signal input unit for receiving an input signal tooutput a first signal through a first node, a ramp voltage generatingunit for generating a ramp voltage on a ramp voltage output node, saidramp voltage generating circuit including a storage capacitor forstoring electric charge on said ramp voltage output node, a dischargingtransistor for responding to said first signal to discharge said rampvoltage output node, and a constant-current source for charging saidramp voltage output node at a constant rate, a comparator for comparingsaid ramp voltage against a voltage setting to output a delayed signalwhich is delayed from said input signal by a delay time corresponding tosaid voltage setting, and a compensating unit for compensating electriccharge flowing from said ramp voltage output node into a parasiticcapacitance of said discharging transistor.
 8. The variable delaycircuit as defined in claim 7 , wherein said signal input unit is adifferential circuit having a pair of complementary output nodesincluding said first node and a second node, and said compensating unitis a compensating capacitor connected between said ramp voltage outputnode and said second node.
 9. The variable delay circuit as defined inclaim 8 , wherein said discharging transistor is a PNP transistor andsaid compensating capacitor is implemented by a p-n junctionreverse-biased between said ramp voltage output node and said secondnode.
 10. The variable delay circuit as defined in claim 9 , whereinsaid p-n junction is implemented by base and emitter of another PNPtransistor having a design size equal to that of said chargingtransistor.
 11. The variable delay circuit as defined in claim 8 ,wherein said discharging transistor is a PMOS transistor.
 12. Thevariable delay circuit as defined in claim 11 , wherein saidcompensating capacitor is implemented by a PMOS capacitor.